The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. Particularly, the present invention is concerned with a technique applicable effectively to a semiconductor integrated circuit device in which elongated element forming regions are formed side by side.
A semiconductor integrated circuit device comprises elements and wiring lines formed on main surfaces of element forming regions (active) each defined by an insulating film. For example, the element forming regions are isolated from each other by an element isolation region. The element isolation region is formed for example by an element isolating film. For example, the element isolating film is formed with use of STI (Shallow Trench Isolation) technique. According to this STI technique, an insulating film such as silicon oxide film is deposited on a trench formed in a semiconductor substrate, then the silicon oxide film present outside the trench is removed, for example, by CMP (Chemical Mechanical Polishing), allowing the silicon oxide film to be buried in the interior of the trench, and the trench with the silicon oxide film thus buried therein is used for the isolation between elements.
For example, a memory LSI (Large Scale Integrated Circuit) such as an Electrically Erasable Programmable Read Only Memory (EEPROM) is formed on each of elongated element forming regions arranged side by side at a certain pitch.
With microstructurization and high integration of memory cell, there is a tendency that such element forming regions become smaller in width and are arranged at a narrower pitch.
As to a flash memory of NOR type with a drain contact formed using what is called SAC (Self-Aligned Contact) technique for coping with the tendency to microstructurization of memory cell, it is described, for example, in IEDM (International Electron Devices Meeting), 1998, pp. 979–982, “A Novel 4.6F2NOR Cell Technology With Lightly Doped Source (LDS) Junction For High Density Flash Memories.”